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8k x 8 bit low power cmos sram features access time :55ns low power consumption: operation current : 15ma (typ.), v cc = 3.0v standby current : 1 a (typ.), v cc = 3.0v wide range power supply : 2.7 ~ 5.5v fully static operation tri-state output data retention voltage : 1.5 v (min.) all products rohs compliant package : 28-pin 600 mil pdip 28-pin 330 mil sop 28-pin 8mm x 13.4mm stsop general description the as6c6264 is a 65,536-bit low power cmos static random access memory organized as 8,192 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the as6c6264 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. the as6c6264 operates with wide ra nge power s upply. functional block diagram de c ode r i/o dat a c ir c uit c ont r ol c ir c uit 8k x8 me mor y ar r ay c olum n i/o a0-a12 v cc v s s dq0-dq7 c e # we # oe # c e 2 pin description symbol description a0 - a12 address inputs dq0 C dq7 data inputs/outputs ce#, ce2 chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection ? fully compatible with all competitors 5v product fully compatible with all competitors 3.3v product all inputs and outputs ttl compatible february 2007 as6c6264 02/feb/07, v1.0 alliance memory inc page 1 of 12
8k x 8 bit low power cmos sram pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss nc vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 as6c6264 pdip/sop 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 ce2 ce# oe# we# s tsop dq3 a11 a9 a8 ce2 dq2 a10 nc a12 a7 a6 a5 vcc dq7 dq6 dq5 dq4 vss dq1 dq0 a0 a1 a2 a4 a3 as6c6264 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 oe# we# ce# absolute maximu m ratings* parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 7.0 v 0 to 70(c grade) t erutarepmet gnitarepo a -40 to 85(i grade) oc t erutarepmet egarots stg -65 to 150 oc p noitapissid rewop d 1 w i tnerruc tuptuo cd out 50 ma soldering temperature (under 10 sec) t solder 260 oc *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliability. truth table mode ce# ce2 oe# we# i/o operation supply current h x x x high-z i sb ,i sb1 standby x l x x high-z i sb ,i sb1 output disable l h h h high-z i cc ,i cc1 read l h l h d out i cc ,i cc1 write l h x l d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. ? page 2 of 12
8k x 8 bit low power cmos sram dc electrical characteristics parameter symbol test condition min. typ. *5 max. unit supply voltage v cc v 5. 2.7 3.0 5 input high voltage v ih *1 v-v2.4 cc +0.3 v input low voltage v il *2 v6.0-5.0- input leakage current i li v cc > = > = > = > = > = v in v ss - 1 - 1 a output leakage current i lo v cc v out v ss, output disabled - 1 - 1 a output high voltage v oh i oh v -0.34.2 am1-= output low voltage v ol i ol = 2ma - - 0.4 v - 55 - 15 45 ma i cc cycle time = min. ce# = v il and ce2 = v ih , i i/o = 0ma average operating power supply current i cc1 cycle time = 1 s ce# Q 0.2v and ce2 R v cc -0.2v, i i/o = 0ma other pins at 0.2v or v cc -0.2v - 3 10 ma -c 1 50 *4 a standby power supply current i sb1 ce# v cc -0.2v or ce2 Q 0.2v -i - 1 80 *4 a notes: c = commercial temperature i = industrial temperature 1. v ih (max) =v cc + 3.0v for pulse width less than 10ns. 2. v il (min) =v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 1 00% tested. 4. 10 a for special request 5. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 o c o c capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note :these parameters are guaranteed by device characterization, but not production tested. ac test conditions votv2.0 slevelesluptupni cc - 0.2v sn3 semitllafdnaesirtupni input and output timing reference levels 1.5v c daoltuptuo l = 50pf + 1ttl, i oh /i ol = -1ma/2ma ? february 2007 as6c6264 02/feb/07, v1.0 alliance memory inc page 3 of 12
8k x 8 bit low power cmos sram ac electrical characteristics (1) read cycle as6c6264-55 parameter sym. min. max. unit read cycle time t rc 55 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe 30 ns chip enable to output in low-z t clz * 10 - ns output enable to output in low-z t olz * 5 - ns chip disable to output in high-z t chz * - 20 ns output disable to output in high-z t ohz * 20 ns output hold from address change t oh 10 - ns (2) write cycle as6c6264-55 parameter sym. min. max. unit write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set-up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overlap t dw 25 - ns data hold from end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high-z t whz * - 20 ns *these parameters are guaranteed by device characterization, but not production tested. ? page 4 of 12
8k x 8 bit low power cmos sram timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid t oh oe# high-z high-z t clz t olz t oe t chz t ohz ce2 t ace ce# t aa address t rc notes : 1.we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low ., ce2 = high . 3.address must be valid prior to or coincident with ce# = low , ce2 = high; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz. ? page 5 of 12
? 8k x 8 bit low power cmos sram write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc ce2 notes : 1.we#, ce# must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#. 3.during a we#controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce#low transition and ce2 high transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. page 6 of 12
8k x 8 bit low power cmos sram data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v or ce2 Q 0.2v 1.5 - 5.5 v data retention current i dr v cc = 1.5v ce# v R cc - 0.2v or ce2 Q 0.2v - 0.5 10 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr R 1.5v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr R 1.5v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vcc(min.) ? page 7 of 12
? 8k x 8 bit low power cmos sram package outline dimension 28 pin 600 mil pdip package outline dimension unit sym. inch.(base) mm(ref) a1 0.010 (min) 0.254 (min) a2 0.1500.005 3.8100.127 b 0.020 (max) 0.508(max) b1 0.055 (max) 1.397(max) c 0.012 (max) 0.304 (max) d 1.430 (max) 36.322 (max) e 0.6 (typ) 15.24 (typ) e1 0.52 (max) 13.208 (max) e 0.100 (typ) 2.540(typ) eb 0.625 (max) 15.87 (max) l 0.180(max) 4.572(max) s 0.06 (max) 1.524 (max) q1 0.08(max) 2.032(max) 15 o (max) 15 o (max) page 8 of 12
? 8k x 8 bit low power cmos sram 28 pin 330 mil sop package outline dimension unit sym. inch(base) mm(ref) a 0.120 (max) 3.048 (max) a1 0.002(min) 0.05(min) a2 0.0980.005 2.4890.127 b 0.016 (typ) 0.406(typ) c 0.010 (typ) 0.254(typ) d 0.728 (max) 18.491 (max) e 0.340 (max) 8.636 (max) e1 0.4650.012 11.8110.305 e 0.050 (typ) 1.270(typ) l 0.05 (max) 1.270 (max) l1 0.0670.008 1.702 0.203 s 0.047 (max) 1.194 (max) y 0.003(max) 0.076(max) 0 o 10 o 0 o 10 o page 9 of 12
8k x 8 bit low power cmos sram 28 pin 8mm x 13.4mm s tsop package outline dimension unit sym. inch(base) mm(ref) a 0.047 (max) 1.20 (max) a1 0.0040.002 0.100.05 a2 0.0390.002 1.000.05 b 0.006 (typ) 0.15(typ) c 0.010 (typ) 0.254(typ) db 0.4650.004 11.800.10 e 0.3150.004 8.000.10 e 0.022 (typ) 0.55(typ) d 0.5280.008 13.400.20 l 0.0200.004 0.500.10 l1 0.03150.004 0.800.10 y 0.08(max) 0.003(max) 0 o 5 o 0 o 5 o note e dimension is not including end flash. the total of both sides end flash is not above 0.3mm. ? february 2007 as6c6264 02/feb/07, v1.0 alliance memory inc page 10 of 12
? 8k x 8 bit low power cmos sram ordering information ordering codes part numbering system as6c 6264 - 55 x x n low power sram prefix device number 6264 access time package options: p = 28 pin 600 mil p-dip s = 28 pin 330 mil sop st = 28 pin stsop (8mm x 13.4 mm) temperature range: c = commercial (0oc to +70o c) i = industrial (-40o to +85o c) n = lead free rohs compliant part february 2007 as6c6264 02/feb/07, v1.0 alliance memory inc page 11 of 12 alliance organization vcc range package operating temp speed ns as6c6264-55pcn 8k x 8 2.7-5.5v 28pin 600mil pdip commercial ~ 0o c to 70o c 55 as6c6264-55scn 8k x 8 2.7-5.5v 28pin 330mil sop commercial ~ 0o c to 70o c 55 as6c6264-55sin 8k x 8 2.7-5.5v 28pin 330mil sop industrial ~ -40oc to 85o c 55 AS6C6264-55STCN 8k x 8 2.7-5.5v 28pin stsop (8 x 13.4 mm) commercial ~ 0o c to 70o c 55 as6c6264-55stin 8k x 8 2.7-5.5v 28pin stsop (8 x 13.4 mm) industrial ~ -40oc to 85o c 55
? alliance memory, inc. 1116 south amphlett , #2, san mateo, ca 94402 tel: 650-525-3737 fax: 650-525-0449 www.alliancememory.com copyright ? alliance memory all rights reserved part number: as6c 6264 document version: v. 1.0 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use. ? february 2007 as6c6264 02/feb/07, v1.0 alliance memory inc page 12 of 12

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